The present invention is related generally to semiconductor manufacturing and Micro Electro Mechanical Systems (MEMS). More specifically, the invention relates to methods for providing thin silicon micromachined structures.
Micro Electro Mechanical Systems (MEMS) often utilize micromachined structures such as beams, slabs, combs, and fingers. These structures can exhibit curvature due to internal stresses and doping gradients. The curvature can be a significant source of error in inertial sensors such as accelerometers, tuning forks, and gyroscopes. Many desired structures have a flatness design criteria that is difficult or impossible to achieve using current processes. In particular, silicon layers heavily doped with boron can have a significant curvature when used in suspended structures.
The aforementioned structures are often made starting with a silicon wafer substrate. A boron-doped silicon epitaxial layer is then grown on the silicon wafer substrate and is subsequently patterned in the desired shape. As is further described below, the boron is used as an etch stop in later processing to allow for easy removal of the silicon substrate, leaving only the thin boron-doped epitaxial layer.
At the interface between the boron-doped epitaxial layer and the silicon substrate, the boron tends to diffuse out of the epitaxial layer and into the silicon substrate. This depletes the epitaxial layer of some boron, and enriches the silicon substrate with boron. The epitaxial layer thus often has a reduced concentration of boron near the interface, which is sometimes called the xe2x80x9cboron tail.xe2x80x9d
After the boron-doped silicon epitaxial layer has been grown to the desired thickness, the silicon substrate is often removed using an etchant that is boron selective. Specifically, the etchant will etch away the silicon substrate, but not the boron-doped silicon epitaxial layer. One such etchant is a solution of ethylene diamine, pyrocatechol, and water (EDP). The etchant typically etches the silicon at a fast rate up to a certain high level boron concentration, at which point the etch rate significantly slows. This high boron concentration level is termed the etch stop level.
The boron concentration near the epitaxial layer surface having the boron tail may be lower than the etch stop level, allowing the etching to remove some of the epitaxial layer surface at a reasonable rate, stopping at the etch stop level of boron concentration beneath the initial surface. The resulting boron-doped structure, such as a beam, thus has two surfaces, the silicon side surface that has the boron tail and the airside surface that has a boron surface layer concentration substantially equal to the concentration in the bulk of the beam away from either surface. Thus, the opposing surfaces have different boron surface layer concentrations.
The building of a suspended element often includes using an epitaxially grown single-crystal silicon heavily doped with boron, for example, greater than ten to the twentieth atoms per cubic centimeter (1020/cm3). In some applications, this doped material may present problems. One problem is an intrinsic tensile stress, which, when the boron-doped layer is relatively thick, can produce severe wafer bow. This wafer bow is incompatible with some fabrication steps. Another problem is that the thickness of the epitaxial layer may be limited due to technological reasons, for example, deposition conditions. Yet another problem is that the Young modulus of the boron-doped material may be lower than that of silicon, and may not be well known and understood.
In addition, the intrinsic losses of the boron-doped material may be higher than those of low-doped silicon. In the lost wafer process, the final release of the mechanical structure is often performed using a long, wet-etching step, which can be based on ethylene-diamine-pyrocathacol (EDP) solution, which requires careful control to maintain industrial hygiene standards during manufacture. What would be desirable is a fabrication process that eliminates the need for highly doped silicon and does not require a wet-etching step using EDP.
The present invention includes methods for making thin silicon cantilevered or suspended structures which can be used to make Micro Electro Mechanical Systems (MEMS). The thin, silicon suspended structure can be used in a number of applications including, for example, accelerometers, gyroscopes, inertial sensing devices and so on. One illustrative embodiment of the present invention begins with a glass wafer and a silicon-on-insulator (SOI) wafer. The SOI wafer includes an insulator layer such as an oxide layer disposed between a first silicon layer and a second silicon layer. The insulator layer may be, for example, a silicon oxide layer.
In one illustrative embodiment, one or more recesses are formed in the glass wafer surface using standard photolithography and etching techniques. After formation of the recesses, electrodes may be formed at least partially within the recesses and, in some embodiments, on the surface of the glass wafer itself, if desired. The electrodes within the recesses may serve as, for example, one plate of a capacitor for sensing distance to, or vibration of, a later added suspended structure disposed over the recess.
The SOI wafer is bonded to the glass wafer, over the recessed and non-recessed portions, using an appropriate method such as anodic bonding, adhesives, heat bonding or any other suitable means. After bonding, the silicon layer of the SOI wafer that is located away from the glass wafer may be removed, using the insulator layer as an etch stop. The insulator layer can then be removed, leaving a single thin silicon layer. A photolithography and etching step can be used to pattern the remaining silicon layer in order to define the desired structure. Preferably, a DRIE process or other suitable process is used to pattern the remaining silicon layer. Suitable structures include tuning forks, combs, and cantilevered structures, among others.
In another illustrative embodiment of the present invention, a glass wafer or substrate, and an SOI wafer with a metal layer on one surface thereof are provided. Like above, and in one illustrative embodiment, the glass wafer may be etched to form a recess or recesses in the glass wafer surface, and electrodes may be formed on the glass wafer surface and/or in the recesses. At least a portion of the metal layer on the SOI wafer is preferably patterned to coincide with the recesses in the glass wafer. The SOI wafer may then be bonded to the glass wafer surface, with the metal layer toward the glass wafer. After bonding, the silicon layer of the SOI wafer that is located away from the glass wafer may be removed, using the insulator layer as an etch stop. The insulator layer is then removed, leaving a single thin silicon layer bonded to the glass wafer.
A photolithographic and DRIE or other suitable process may then be used to etch the remaining silicon layer into a desired pattern, preferably in the region above the patterned metal layer. The etchant is preferably selected to etch through the remaining silicon layer but not through the underlying metal layer. The metal layer thus may act as an etch stop. The metal layer is believed to allow for sharper feature definition at the silicon-metalization layer interface, and also provides a barrier during the silicon etch step that may prevent gases in the recesses from escaping into the atmosphere, such as into a DRIE chamber. After etching of the remaining silicon layer, the metal layer may be removed using standard etching techniques.